科锐国际代招：上海知名500强外资通信公司招DSP/FPGA职位

Position: FPGA Design Engineer, Senior Design Engineer   -- RTSW_F
Responsibilities:
 Responsible for FPGA design, development and verification in Wireless baseband system.
 Take charge of project analysis and FPGA chip select.
 Verification and test on board.
 Support and solve problems in system test.
Requirements:
 Good knowledge of Wireless Communication systems.
 Experience on baseband protocol and algorithm is a plus.
 Excellent knowledge of digital circuit, logical design and timing analysis.
 2+ years with VHDL/Verilog programming in FPGA.
 Familiar with Modelsim, ISE and others necessary EDA tools.
 Familiar with tcl / perl, familiar with Linux.
 Language ability: English, good, both written and oral.

Position: DSP Design Engineer, Senior Design Engineer   -- RTSW_D
Job description :
 Responsible for the DSP design, simulation and maintenance in Wireless system.
 Carry out the assigned tasks and report progress to project manager.
 Take charge of project analysis and DSP chip select.
 Coding, verification, and test on board.
 Solve troubles in product development.
Requirement:
 Good knowledge of Wireless Communication systems and good understanding of telecom industry.
 2+ working years for Freescale DSP (8156, 8157 prefer), or TI DSP C64x.
 2+ working years for DSP drivers (SRIO etc).
 Wireless link level simulation knowledge with Matlab or C language is a plus.
 Education background: Bachelor or above. Major in electronic engineering, telecommunication, computer science, or
related
 Good interpersonal skills, communication, team work.
 Language ability: English, good, both written and oral, CET-6.
 Other requirements: Capability to adapt rapidly in a challenging job environment; team work capabilities


如需进一步了解，请将简历发至我的邮箱或通过MSN联系，具体如下：
邮箱：celiatian@careerrpo.com
MSN:tyserena@hotmail.com