Cypress CY8CKIT-017 CAN－LIN总线连接解决方案

Cypress公司的CY8CKIT－017 CAN/LIN扩展板(EBK)能和CY8CKIT－001 PSoC®开发板(DVK),CY8CKIT－030 PSoC 3开发板(DVK)配合使用,评估PSoC 3 和PSoC 5器件的CAN通信能力.本文介绍了PSoC 5器件CY8C52主要特性,方框图, CY8CKIT－017 CAN/LIN扩展板(EBK)特性,电路图和材料清单.

With its unique array of configurable blocks, PSoC® 5 is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C52 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

CY8C52主要特性:

 32-bit ARM Cortex-M3 CPU core

 DC to 40 MHz operation

 Flash program memory, up to 256 KB, 100,000 write cycles, 20-year retention and multiple security features

 Up to 64 KB SRAM memory

 128 bytes of cache memory

 2-KB electrically erasable programmable read-only memory (EEPROM) memory, 1 million cycles, and 20 years retention

 24-channel direct memory access (DMA) with multilayer AMBA high-performance bus (AHB) bus access

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

 Low voltage, ultra low power

 Operating voltage range: 2.7 V to 5.5 V

 6 mA at 6 MHz

 Low power modes including:

• 1-μA sleep mode

• 0.15-μA hibernate mode with RAM retention

 Versatile I/O system

 46 to 70 I/Os (60 GPIOs, 8 SIOs, 2 USBIOs))

 Any GPIO to any digital or analog peripheral routability

 LCD direct drive from any GPIO, up to 46 × 16 segments

 CapSense® support from any GPIO

 1.2 V to 5.5 V I/O interface voltages, up to four domains

 Maskable, independent IRQ on any pin or port

 Schmitt trigger transistor-transistor logic (TTL) inputs

 All GPIOs configurable as open drain high/low, pull up/down, High-Z, or strong output

 25 mA sink on SIO

 Digital peripherals

 20 to 24 programmable logic device (PLD) based universal digital blocks (UDBs)

 Full-Speed (FS) USB 2.0 12 Mbps using a 24 MHz external oscillator

 Four 16-bit configurable timer, counter, and PWM blocks

 Library of standard peripherals

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• SPI, UART, and I2C

• Many others available in catalog

 Library of advanced peripherals

• Cyclic redundancy check (CRC)

• Pseudo random sequence (PRS) generator

• Local interconnect network (LIN) bus 2.0

• Quadrature decoder

 Analog peripherals (2.7 V  VDDA  5.5 V)

 1.024 V ±1% internal voltage reference

 Successive approximation register (SAR) analog-to-digital converter (ADC), 12-bit at 700 ksps

 One 8-bit, 5.5-Msps current DAC (IDAC) or 1-Msps voltage DAC (VDAC)

 Two comparators with 95-ns response time

 CapSense support

 Programming, debug, and trace

 Serial wire debug (SWD) and single-wire viewer (SWV) interfaces

 Cortex-M3 flash patch and breakpoint (FPB) block

 Cortex-M3 data watchpoint and trace (DWT) generates data trace information

 Cortex-M3 Instrumentation Trace Macrocell (ITM) can be used for printf-style debugging

 DWT and ITM blocks communicate with off-chip debug and trace systems via the SWV interface

 Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces

 Precision, programmable clocking

 3 to 24 MHz internal oscillator over full temperature and voltage range

 4 to 25 MHz crystal oscillator for crystal PPM accuracy

 Internal PLL clock generation up to 40 MHz

 32.768 kHz watch crystal oscillator

 Low power internal oscillator at 1, 33, and 100 kHz

 Temperature and packaging

 –40 °C to +85 °C degrees industrial temperature

 68-pin QFN and 100-pin TQFP package options


图1. CY8C52简化框图

CY8CKIT-017 CAN/LIN扩展板(EBK)

The CY8CKIT-017 CAN/LIN Expansion Board Kit (EBK) is an expansion board that is used with the CY8CKIT-001 PSoC® Development Kit (DVK), the CY8CKIT-030 PSoC 3 Development Kit (DVK), or the CY3280-22x45 Universal CapSense® Controller (UCC) kit. It enables you to evaluate the Controller Area Network (CAN) communication capability of PSoC 3 and PSoC 5 devices. You can design your own projects with an easy-to-use CAN component in Cypress’s PSoC Creator™ software, or by altering code examples provided with this kit.

This kit also allows you to develop custom Local Interconnect Network (LIN) communication IP for any PSoC device (PSoC 1, PSoC 3, or PSoC 5). Currently no LIN user modules, components, or code examples are provided by this kit or with Cypress software. However, these LIN solutions are planned for the future.

The CY8CKIT-017 CAN/LIN EBK is used with the PSoC family of devices. PSoC 3 is a programmable system-on-chip platform for 8-, 16-, and 32-bit applications. It combines precision analog and digital logic with a high-performance 8051 single cycle per instruction pipelined processor, achieving 10 times the performance of previous 8051 processors. With PSoC, you can create the exact combination of peripherals and integrated proprietary IP to meet the needs of your applications.

This kit is also compatible with the CY8CKIT-030 PSoC 3 Development Kit. See the documentation for the CY8CKIT-030 DVK to see which ports this EBK can be attached to. A CY8CKIT-030 kit can generally be substituted for a CY8CKIT-001 kit when using the CY8CKIT-017 kit. Therefore, any information regarding the CY8CKIT-001 kit in this document generally also applies to the CY8CKIT- 030 kit.

This kit can also interface with the CY3280-22x45 Universal CapSense Controller (UCC) kit for CY8C2xx45 PSoC 1 devices. This EBK can add LIN capabilities to the UCC kit. However, it does not add CAN capabilities to this kit, because PSoC 1 devices do not have CAN hardware.

CY8CKIT-017 CAN/LIN扩展板(EBK)包括:

■ CAN/LIN Expansion Board

■ Quick Start Guide

■ Kit CD

图3.带CY8CKIT-001 DVK 的CY8CKIT-017 CAN/LIN扩展板(EBK)外形图

图4. CY8CKIT-017 CAN/LIN扩展板(EBK)电路图
CY8CKIT-017 CAN/LIN扩展板(EBK)材料清单:

详情请见:
61507和
61508