sr.staff asic design engineer

NO.54-【猎头职位：上海需要一位  sr.staff asic design engineer】联系人：Grace-Tai,邮箱：hr@kthr.com，微信也可查询职位了！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！Job Description:Ø  Provide technology IPintegration support to QC JV partners throughout their SOC development.Ø  Liaison between ***engineering teams, 3rd party vendors, and JV engineering teams to architect,integrate and validate the design that meets the partners acceptance criteria.Ø  Maintains regularcommunication with key stakeholders to ensure continued alignment between teamdeliverables and product execution plan.Ø  Prepare engineeringcollaterals from *** IP engineering teams, include externalization of docs,simulation models, test benches, test patterns, design databases, andsupporting tools, utilities and scripts.Ø  Use EDA tools to validatethe package content where necessary.Ø  Deliver the engineeringcollaterals thru approved systems.Ø  Assist partners in IPintegration.Ø  Use deductive and inductiveproblem solving approach, debug functional models and functional vectorsrelated to complex customer test cases including but not limited to powersequencing, concurrency, memory contention, and system throughput.Ø  Create an emulationenvironment for JV partners to validate the combined system SOC.Ø  Assist partners in physicalimplementation.Ø  Align design metricsbetween the IP and the SOC (corners, views, process POR ..etc)Ø  Facilitate exchangesbetween *** engineering, JV partners, foundry design services and 3rd Party IPvendors.Ø  Optimize JV SOC floorplanusing various *** IP layout.Ø  Resolve boundary issuesincluding timing and LVS/DRC.Ø  Assist partners inproductization. Provide onsite bring up support related to *** technology IP.Ø  Act as a principle leadrepresenting *** engineering team, effectively utilizes advanced problemsolving and SOC engineering practices to resolve complex architecture, design,or verification problems.Ø  Extensive system debugexperience is required.Job Requirement:1）MinimumQualificationsBachelor'sdegree in Science, Engineering, or related field.7+years ASIC design, verification, or related work experience.2）PreferredQualifications  Minimumqualification includes 7 to 12 years of SOC design experience in Logic Design,VHDL, Verilog & SV (SystemVerilog) RTL, verification/emulation, synthesis,LINT and static timing analysis, clock domain crossingtechniques/implementation. Strong understanding of chip integrationmethodologies & flows. Solid background in scripting for automation ofdesign methodologies & flows is desired. Detail oriented with strongorganizational, exceptional problem solving, and great communication skills(both written and oral). Fluent in English and Mandarin is a must. Ability towork in a highly collaborative fast-paced team environment is required. Strongmobile knowledge is highly desired.3）EducationRequirements        BSc,electrical engineering is requiredMSc,electrical engineering is desired福利：极具竞争力的薪资，五险一金，优裕的年假制度，世界顶尖团队合作机会