上海需要若干位 Senior Staff SOC Design Engineer(Low Power)

【猎头职位:上海需要若干位 Senior Staff SOC Design Engineer(Low Power)】联系人：David-Chen，邮箱：hr@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！
工作内容职位描述：
根据DE提供的RTL,release符合要求的网表文件以及相应的约束文件,并且协助PR team timing signoff.具体工作包括 synthesis, DFT, formal check，low power check, SDC generation, STA signoff.


任职资格：
1. 电子工程,微电子，半导体以及相关领域的本科硕士博士。
2. 需要5年以下工作经验：
Proficiency in all following technology logic synthesis ,DFT,formal check and STA
expert for at least one area, such as timing , DFT, power, signoff.
Proficiency in related EDA tools.
Proficiency in Verilog language.
Experience with logic design and simulation.
Experience with 40nm or 28nm process is a plus.
Good knowledge of SOC design is a plus.
Self-motivated and good team player.