上海需要三位 Automatic Placement and Routing (APR) Engineer

【猎头职位：上海需要三位 Automatic Placement and Routing (APR) Engineer】联系人：Raymond-Chen，邮箱：hr@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！Responsibilities:1.Be responsible for advanced chip implementation flow development, chip PPA boost, and support headquarter advanced technology for EDA router engagement; 2.ASIC block-level implementation and/or full-chip integration projects; 3.Develop IC design methodology.
Requirement:
1.MS or BS in CS, EE related field withexperience in APR, physical verification, chip implementation, or CAD algorithm;
2.Expert in ASIC RTL-to-GDS design flow;
3.Solid skill sets of Cadence/Synopsys/MentorEDA tools;
4.Experience with TSMC 40nm technology;
5.Experience in implementation signoff;
6.Proven record in production tapeouts;
7.Experience in tapeout with multi-million gatescount SOC design. 28nm/40nm design experience is a plus;
8.Capable of executing timing budgeting, synthesis,P&R, CTS, timing closure, DFT, physical verification, DFM and spicesimulations;
9.Experience in CAD methodology and problemsolving skill;
10.Familiar with Verilog, Perl/Tcl and C/C++;
11.Good communication in English.