新加坡急需Digital Design Engineers for Mixed-Signal Power Management ASICs

【猎头职位：新加坡需要一位“Digital Design Engineers for Mixed-Signal Power Management ASICs ”】职位关键词：digital design, max-singnal, PMIC, 联系人：Susan，MSN:lushan630@hotmail.com；Skype:susan.lu63；Email: susan-lu@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！关注成功后输入”KT“即可查询职位！



Skills/Experience
Design candidates will have a minimum of 2-3 years of relevant experience and must have detailed knowledge of digital ASIC design including architecture, RTL design for control and signal processing functions, linting, synthesis, STA, and DFT. Design candidates must also have experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence. Experience designing mixed signal interfaces and integrating digital modules into mixed-signal ASICs is desirable. Verification candidates should have a minimum of 2-3 years of relevant experience and must have detailed knowledge of self-checking testbench architectures (including directed and random-constrained generation) and coverage-driven verification techniques at the functional, assertion and code levels. Verification candidates will also have a working understanding of Object Oriented System Verilog principles. Experience with VMM, OVM, or UVM is desirable as is experience verifying digital modules in mixed-signal ASICs.

Responsibilities
Successful candidates will be responsible for leading, and participating in, the design and verification of leading edge ASICs in advanced digital CMOS processes for multi-function mobile platforms.

Education Requirements
Bachelor's degree in Electrical Engineering required. Master's degree in Electrical Engineering preferred.

Interested individual please contact with Susan Lu for further confidential discussion via:
Tel: +86(21)61023600 * 808
M/B:15902188625
Email: susan-lu@kthr.com

* Your private information will be treated in strict confidence and used only for recruitment purpose. Thanks.