成都需要一位 Senior IP Design Engineer
2015年09月22日 13:41 发布者:KT咨询
【猎头职位:成都需要一位 Senior IP Design Engineer】联系人:Judy-Wu,邮箱:hr@kthr.com,微信也可查询职位啦!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加,欢迎大家关注!Responsibility:
Write/define the IP design Specification and architecture;
RTL coding for the design with Verilog;
Design rule check for the RTL design;
Setup the sim environment, add test patterns, do regression test and code coverage analysis;
Do IP level Synthesis, STA and DFT, and review the logs to improve the design;
Release the design database for whole chip integration and do integration support;
Write the complete design reports;
Chip validation of the related modules.
Qualification:
MSEE with minimum 2-year experience of digital design experience;
Solid knowledge of logic and circuit design;
Strong skills of Verilog RTL coding, verification and debug, and familiar with the design/verification flow;
Familiar with the microprocessors and computer system architecture;
Familiar with Synthesis, STA, DFT and ATPG flow;
Familiar with FPGA emulation flow;
Related experience of high-speed interface( such as Ethernet, USB, HDMI, etc.) or on-chip-bus backbone design is a big plus;
Familiar with Perl/Python, shell programming and excel operation is a plus;
Excellent interpersonal and communication skills, good teamwork adaptability, good written English skills, self-motivated.