Verilog编程问题

我在编写FFT内核的时候在大循环里总是出现下面的错误
Error (10119): Verilog HDL Loop Statement error at Test.v(72): loop with non-constant loop condition must terminate within 250 iterations
Verilog不能支持250层以上的循环么？求高手指教。
有没有现成的FFT内核，希望能参考一下。

一下为代码
/*
FFT code
*/
module Test(CLK_50M,REST,CS,ADCDAT,FULL,BUSY,EXT,OUTDAT);
input CLK_50M,REST,CS,EXT;
input ADCDAT;
output FULL,BUSY;
output OUTDAT;//计算结果是浮点型
//reg ADCDAT;
reg OUTDAT;
reg FULL,BUSY;
reg CNT;
reg N;
reg CLK;
reg ADCMEMORY;//输入为实数
reg DOREMEMORY,DOIMMEMORY;//输出为复数
reg i,j,k;//中间过程变量寄存器
reg f,m,l,le,lei,ip;
reg temp;
reg u,v,w;//x=real,x=image
parameter FFTN=16'd256,//FFT点数
    Pi=3.14159,//pi
    ADCBit=4'd8,//8bit ADC
    CLKDiv=16'd50;//1MHz
   
always @(posedge CLK_50M or negedge REST)
if(!REST) CNT <= 16'h0000;
else if((!CS)&&(CNT!=CLKDiv)) CNT <= CNT+1'b1;
   else CNT <= 16'h0000;
always @(posedge CLK_50M or negedge REST)
if(!REST) CLK <= 1'b0;
else if(CNT==CLKDiv) CLK <= ~CLK;

always @(posedge CLK or negedge REST)//ACD数据输入
if(!REST) N <= 16'h0000;
else if(!CS) begin ADCMEMORY <= ADCDAT;N <= N+1'b1; end

always @(N)
if(N==FFTN-1) FULL <= 1'b1;
else FULL <= 1'b0;

always @(posedge CLK_50M or negedge REST)
if(!REST) begin BUSY <= 1'b0;j <= 16'h0000;f <= FFTN/16'd2; end
else if(N==FFTN-1)
  begin
   BUSY <= 1'b1;
   for(i=16'h0000;i     begin
     if(i       begin
       temp <= ADCMEMORY;
       ADCMEMORY <= ADCMEMORY;
       ADCMEMORY <= temp;
      end
     k <= FFTN/16'd2;
     while(k<=j)
      begin
       j <= j-k;
       k <= k/16'd2;
      end
     j <= j+k;
    end
   for(i=16'h0000;i     begin
     DOREMEMORY <= ADCMEMORY;
     DOIMMEMORY <= 0;
    end
   for(l=16'd1;f!=16'd1;l=l+1'b1) f <= f/2;
   for(m=16'd1;m<=l;m=m+1'b1)
    begin
     le <= 16'd2<<(m-1);
     lei <= le/2;
     u <= 16'd1;
     u <= 16'd0;
     w <= cos(Pi/lei);
     w <= -sin(Pi/lei);
     for(j=0;j<=lei-1;j=j+1'b1)
      begin
       ip <= i+lei;
       EE(DOREMEMORY,DOIMMEMORY,u,u,v,v);
       DOREMEMORY <= DOREMEMORY-v;
       DOIMMEMORY <= DOIMMEMORY-v;
       DOREMEMORY <= DOREMEMORY+v;
       DOIMMEMORY <= DOIMMEMORY+v;
      end
     EE(u,u,w,w,u,u);
    end
   BUSY <= 1'b0;
  end
  
always @(posedge CLK or posedge EXT or negedge BUSY or negedge CS)
if((!CS)&&(!BUSY)&&EXT)
  begin
   OUTDAT <= {DOIMMEMORY,DOREMEMORY};
   N <= N-1'b1;
  end
//task EE(ARE,AIM,BRE,BIM,CRE,CIM);
task EE;
input ARE,AIM,BRE,BIM;
output CRE,CIM;
begin
CRE=ARE*BRE-AIM*BIM;
CIM=ARE*BIM+AIM*BRE;
end
endtask
endmodule