台积电 12-bit 64MHz 1.8V Pipeline ADC资料

1. Features

· 12/10-bit Resolution (configurable)
· 64/32 MHz Conversion Rate
· 1.5Vpp Differential Input
· 1.8V ±10% Power Supply
· Power down capability
· Internal References Generator
· Power Dissipation: 40mW ±10% @ 32Ms/s
85mW ±10% @
64Ms/s
· Core Cell Area: <0.8mm2

2. General Description

The AD1264tg is a fully differential high-speed lowpower pipelined ADC core cell designed for TSMC 0.18um (sige) 3P6M + MiM CMOS technology using only standard CMOS process devices. The ADC architecture employs 11 multi-bit pipelined stages to achieve sampling rates above 64 MS/s with low power dissipation. Digital error correction is employed to reduce DNL errors.

The references voltages are internally generated from an external bandgap and are provided outside for decoupling purposes. It includes an adjustable bias current generation to minimize power dissipation at lower frequency operation.

A power down capability is included for extremely low power dissipation in stand-by mode. This ADC is suitable for applications requiring medium resolutions and high-speed conversion rates, such as video, imaging, data acquisition, high-speed data transmission and communications.

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