ZT: Addressing system-level ESD questions

Addressing system-level ESD questions

As semiconductor manufacturers introduce new wireline transmission devices built on smaller CMOS geometries, more circuit protection challenges are emerging. This article explores five frequently asked questions regarding the basics of ESD and transient voltage suppression for board level circuit protection on dataline communication circuits.
The challenge of protecting today's systems from transient threats is more complex than ever before. However, careful selection of low-clamping voltage TVS components and paying attention to a clean layout can ensure that a system is adequately safeguarded against electrical transient threats. View the PDF document for more information.