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//***********************************************************
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//¿É×ۺϵÄ״̬»úÉè¼ÆµÄµäÐÍ·½·¨
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//ʵÏÖµäÐ͵Ä״̬»úÉè¼Æ
//************************Сī±Ê¼Ç£¬Áô×÷»ØÒä**********************
module fsm (clk,rst_n,A,k1,k2,State);
input clk;
input rst_n;
input A;
output k1,k2;
output State;
reg k1;
reg k2;
reg State; //µ±Ç°×´Ì¬¼Ä´æÆ÷
parameter Idle = 2'b00,
Start = 2'b01,
Stop = 2'b10,
Clear = 2'b11; //±àÂë £¬×¢Ò⣬ֻÓÐÔÚ×îºóÒ»¾äÓ÷ֺţ¬ÆäËûµØ·½ÓöººÅ
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
State <= Idle;
k1 <=1'b0;
k2 <=1'b0;
end
else case (State) //״̬ÅжÏÓë×éºÏÂß¼¸³Öµ
Idle :if(A) begin
State <= Start;
k1 <= 0;
end
else begin
State <= Idle;
k1 <= 0;
k2 <= 0;
end
Start :if(!A) State <= Stop;
else State <= Start;
Stop :if(A) begin
State <=Clear;
k2 <= 1;
end
else State <= Stop;
Clear :if(!A) begin
State <= Clear;
k2 <= 0;
k1 <= 1;
end
else State <= Clear;
default : State <= 2'bxx; //¸æËß×ÛºÏÆ÷ caseÓï¾äÒѾָ¶¨ÁËËùÓÐ״̬£¬ÕâÑù×ÛºÏÆ÷¾Í»áɾ³ý²»ÐèÒªµÄÒëÂëµç·£¬Ê¹Éú³ÉµÄµç·¼òµ¥
endcase
endmodule
//************************СīƷÅÆ£¬ÄãÖµµÃÓµÓÐ~**************************
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//***********************************************************
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//ÓÉÊä³öÖ¸¶¨µÄÂë±íʾ״̬µÄ״̬»ú
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//ÓÃÓÚ¸ßËÙ״̬»úµÄÉè¼Æ
//************************Сī±Ê¼Ç£¬Áô×÷»ØÒä**********************
module fsm2(clk,rst_n,A,k1,k2,State);
input clk;
input rst_n;
input A;
output k1,k2;
output State;
reg State; //µ±Ç°×´Ì¬¼Ä´æÆ÷
assign k1 =State;
assign k2 =State;
parameter Idle = 5'b00000, //²ÉÓö¾ÈȱàÂ루ÿ¸ö״ֻ̬ÓÐÒ»¸ö¼Ä´æÆ÷ÖÃλµÄ״̬»úÕâÑùÓõÄ×éºÏµç·ʡһЩ£¬¶øÇÒËÙ¶ÈÒ²¿ì£©
Start = 5'b00010,
Stop = 5'b00100,
StoptoClear = 5'b11000,
Clear = 5'b01010,
CleartoIdle = 5'b00111; //±àÂë £¬×¢Ò⣬ֻÓÐÔÚ×îºóÒ»¾äÓ÷ֺţ¬ÆäËûµØ·½ÓöººÅ
always @(posedge clk or negedge rst_n)
if(!rst_n)
State <= Idle;
else case (State) //״̬ÅжÏÓë×éºÏÂß¼¸³Öµ
Idle :if(A)
State <= Start;
else
State <= Idle;
Start :if(!A) State <= Stop;
else State <= Start;
Stop :if(A)
State <=StoptoClear;
else State <= Stop;
StoptoClear :State <= Stop;
Clear :if(!A)
State <= Clear;
else State <= Clear;
CleartoIdle :State <= Idle;
default : State <= Idle;//¸æËß×ÛºÏÆ÷ caseÓï¾äÒѾָ¶¨ÁËËùÓÐ״̬£¬ÕâÑù×ÛºÏÆ÷¾Í»áɾ³ý²»ÐèÒªµÄÒëÂëµç·£¬Ê¹Éú³ÉµÄµç·¼òµ¥
endcase
endmodule
//************************СīƷÅÆ£¬ÄãÖµµÃÓµÓÐ~**************************
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//***********************************************************
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//¶àÊä³ö״̬ʱµÄ״̬»ú
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//************************Сī±Ê¼Ç£¬Áô×÷»ØÒä**********************
module fsm3 (clk,rst_n,A,k1,k2,state);
input clk,rst_n,A;
output k1,k2;
output state;
reg k1,k2;
reg state;
reg xiaomo;
parameter Idle = 2'b00,
start = 2'b01,
stop = 2'b10,
clear = 2'b11;
always @ (posedge clk or negedge rst_n)
if(!rst_n) state <= Idle;
else state <= xiaomo; //ÿһ¸öʱÖÓ²úÉúÒ»¸ö¿ÉÄܵı仯£¬¼´Ê±ÐòÂß¼²¿·Ö
always @ (state or A) //×éºÏÂß¼²¿·Ö
begin
case (state)
Idle : if(A) xiaomo = start;
else iaomo = Idle;
start : if(!A)xiaomo = stop;
else iaomo = start;
stop : if(A)xiaomo = clear;
else iaomo = stop;
clear : if(!A) xiaomo =Idle;
else iaomo = clear;
default : xiaomo = 2'bxx;
endcase
end
always @ (state or A or rst_n) //²úÉúÊä³ök1µÄ×éºÏÂß¼
if(!rst_n) k1=0;
else if(state ==clear && !A)
k1=1;
else k1=0;
always @(state or A or rst_n) //²úÉúÊä³ök2µÄ×éºÏÂß¼
if(!rst_n) k2=0;
else if(state ==stop && A)
k2=1;
else k2=0;
endmodule
//************************СīƷÅÆ£¬ÄãÖµµÃÓµÓÐ~**************************